View HDCS-1020_212572.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Agilent HDCS-1020, HDCS-2020 CMOS Image Sensors
Data Sheet
Key Specifications and Features * Available in two image array sizes: VGA (640 x 480) and CIF (352 x 288) * RGB Bayer color filter array * Independent X and Y sub-sampling modes (2:1 each) providing up to a 4X frame rate increase Description The HDCS-1020 and HDCS-2020 CMOS Image Sensors capture high quality, low noise images while consuming very low power. These parts integrate a highly sensitive active pixel photodiode array with timing control and onboard A/D conversion. Available in either VGA (640 x 480) or CIF (352 x 288) resolution image arrays, the devices are ideally suited for a wide variety of applications. The HDCS-2020 and HDCS-1020, when coupled with Agilent's HDCP family of image processors, provide a complete imaging system to enable rapid endproduct development. Designed for low-cost consumer electronic applications, the HDCS-2020 and HDCS-1020 sensors deliver unparalleled performance for mainstream imaging applications. HDCS-2020 (VGA) and HDCS-1020 (CIF) are CMOS active pixel image sensors with integrated A/D conversion and full timing control. They provide random access of sensor pixels, which allows windowing and panning capabilities. The sensor is designed for video conferencing applications and still image capabilities. The HDCS family achieves excellent image quality with very low dark current, high sensitivity, and superior antiblooming characteristics. The devices operate from a single DC bias voltage, are easy to configure and control, and feature low power consumption. Programmable Features * Programmable window size ranging from the full array down to a 4 x 4 pixel window * Programmable panning capability which allows a specified window (minimum 4 x 4 pixels) to be located anywhere on the sensor array * Integrated programmable gain amplifiers with independent gain control for each color (R, G, B) * Internal register set programmable via either the UART or synchronous serial interface * Integrated timing controller with rolling electronic shutter, row/ column addressing, and operating mode selection with programmable exposure control, frame rate, and data rate * Programmable horizontal, vertical, and shutter synchronization signals * Programmable horizontal and vertical blanking intervals * HDCS-1020 Full frame video rate at 8 bit resolution: 30 fps CIF at 32 MHz and 25.8 fps at 25 MHz * HDCS-2020 Full frame video rates at 10 bit resolution: 15 fps VGA at 25 MHz * Still image capability * Mechanical shutter and external flash mode * Low power modes * Shadow gain and exposure registers * Integrated analog to digital converters: HDCS-2020 (10 bit), HDCS-1020 (8 bit) * Automatic subtraction of column fixed pattern noise * Integrated voltage references * Digital image data output via 8 bit (HDCS-1020) and 10 bit (HDCS-2020) synchronous parallel interface or serial interface Applications * Digital still cameras * PC cameras * Handheld computers * Cellular phones * Notebook computers * Toys
Introduction to Sensor Use
The sensor acts as a normal CMOS digital device from the outside. Internal circuits are a combination of sensitive analog and timing circuits. Therefore, the designer must pay attention to the PC board layout and power supply design. Writing to registers via an I2C compatible two-wire interface provides control of the sensor. Sensor data is normally output via an 8 or 10 bit parallel interface (serial data output is also available). Once the registers are programmed the sensor is selfclocking and all timing is internally generated. On chip programmable amplifiers provide a way to separately adjust the red green and blue pixels for a good white balance. Analog to digital conversion is also on chip and 8 or 10 bit digital data is output. A data ready pulse follows each valid pixel output. An end of row signal follows each row and an end of frame signal follows each frame. PCB Layout Analog Vdd and analog ground need to be routed separately from digital Vdd and digital ground. Noisy circuits or ICs should not be placed on the opposite side of the PC board. Heat producing circuits such as microprocessors or LCD
displays should not be placed next to or opposite from the sensor to reduce noise in the image. Power Supply The sensor operates at 3.3 VDC. There are two power supplies for the sensor, analog Vdd and digital Vdd. The two supplies and grounds must be kept separate. Two separate regulators provide the best isolation. Any noise on the analog supply will result in noise in the image. Analog and digital ground should be tied together at a single point of lowest impedance and noise. Master Clock The part requires a 50% duty cycle master clock. Maximum clock rates are 25 MHz for HDCS-2020 and 32 MHz for HDCS-1020. Reset A hard reset is required before the sensor will function properly. Once the master clock is running, assert nRST_nSTBY for 40 clock cycles. Register Communication Communication (read/write) to the sensor registers is via a two wire serial interface-- either a synchronous I2C compatible or
half duplex UART (9600 baud default). nTristate (pin 15 HDCS-1020 only) must be pulled high for normal operation. The HDCS-2020 does not have nTristate. Parallel Data Output 8 or 10 bit parallel data is output from the sensor. A data ready line (DRDY) is asserted when the data is valid. The sensor acts as a master in the way it outputs data. There is no flow control or data received handshake. Once the RUN bit (CONTROL register) is set, the image processor must be ready to accept data at the sensor rate and when the data is presented. Serial Data Output In this mode, output data lines D0 and D1 (the lower two bits of the parallel data port) act as a two wire serial interface. Handshaking At the end of one row of data, the nROW line is asserted. At the end of one frame of data, the nFRAME_nSYNC line is asserted. Registers The following is a table of sample register settings. These values are a good starting point.
2
Table 1. Register Set Declaration.
Register Name
Identifications Register Status Register Interrupt Mask Register Pad Control Register Pad Drive Control Register Interface Control Register Interface Timing Register Baud Fraction Register Baud Rate Register ADC Control Register First Window Row Register First Window Column Register Last Window Row Register Last Window Column Register Timing Control Register PGA Gain Register: Green PGA Gain Register: Red PGA Gain Register: Blue PGA Gain Register: Green Row Exposure Low Register Row Exposure High Register Sub-Row Exposure Register Error Control Register Interface Timing 2 Register Interface Control 2 Register Horizontal Blank Register Vertical Blank Register Configuration Register Control Register Reserved Reserved Reserved Reserved
Mnemonic
IDENT STATUS IMASK PCTRL PDRV ICTRL ITMG BFRAC BRATE ADCCTRL FWROW FWCOL LWROW LWCOL TCTRL ERECPGA EROCPGA ORECPGA OROCPGA ROWEXPL ROWEXPH SROWEXP ERROR ITMG2 ICTRL2 HBLANK VBLANK CONFIG CONTROL
Address (hex)
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20
Sample Value (hex)
0x7F 0x00 0x03 0x00 0x20 0x00 0x00 0x00 0x08 0x00 0x07 0x79 0xA8 0x04 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x4B 0x00 0x00 0x00 0x0C 0x04 -- -- -- --
3
Setting Exposure and Gain The exposure of an image is a function of the exposure and gain registers. Exposure sets the length of time each pixel integrates the light (shutter speed). Gain settings allow pixel values to be amplified. Gain values from 1x to 40x are allowed, but higher gain settings amplify noise (much like higher ISO film speeds are grainier). It is best to use the lower gain settings for better images. Gains from 1x to 10x are generally recommended. Note there are two green gain registers listed in Table 2, one for the odd number row green pixels and one for the even number row green pixels. The green color filters can be slightly different between rows and this allows finetuning. Using the same gain setting for both green registers is usually enough. Since the blue channel is not as sensitive, using blue gains approximately double that of red and green will allow the A/D full range on all three channels. Using a MacBeth Color Checker is a good way to judge exposure and color balance. A good raw image will have a good grey scale (the bottom patches on the chart). Gain settings should be adjusted so the red, green, and blue values are equal on any one grey patch. After setting gain, the exposure registers should be adjusted for a good exposure. There are three exposure registers; see Table 3.
Table 2.
Register Name
PGA Gain Register: Green PGA Gain Register: Red PGA Gain Register: Blue PGA Gain Register: Green
Mnemonic
ERECPGA EROCPGA ORECPGA OROCPGA
Address (hex)
0x0F 0x10 0x11 0x12
Table 3.
Register Name
Row Exposure Low Register Row Exposure High Register Sub-Row Exposure Register
Mnemonic
ROWEXPL ROWEXPH SROWEXP
Address (hex)
0x13 0x14 0x15
The row exposure high register (upper 8 bits) and row exposure low register (lower 8 bits) act as a single 16 bit register. This 16 bit register sets the integration time (shutter speed) of the sensor. The sub-row exposure register is used for very small changes to exposure and allow fine-tuning for exact shutter speeds. Proper exposure will result in black values near 0x00 and white values near 0xFF (assuming 8 bits). All six grey patches on the MacBeth chart should have different average intensity values in the image. If the two brightest patches both appear white then the exposure is too long. If the two darkest patches both appear black then the exposure is too short. Remember that the raw image does not have gamma correction applied yet. The final grey scale image needs to be evaluated after gamma correction.
Image Processing The raw data from the sensor requires image processing before a digital image is ready for viewing. Some standard steps of image processing are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Defective pixel correction Lens flare subtraction Auto-exposure Auto-white balance Color filter array interpolation (demosaic) Color correction (3x3 matrix) Gamma correction Color space correction (3x3 matrix) Data compression
Image processing is not part of the sensor and must be supplied separately. Image processors that are compatible with these sensors are available from Agilent Technologies (HDCP-2000, HDCP-2010).
4
Typical Application
30 MHz Clock
7 Clk 24 IMODE0 23 IMODE1 Vdd 10K 25 nTRISTATE D0 D1 D2 D3 D4 D5 D6 D7 DRDY 14 13 10 9 8 1 32 31 6 25 26 21 30 29 D0 D1 D2 D3 D4 D5 D6 D7 DATA READY Reset End of Row End of Frame TxD/RxD Clock
Parallel Interface
HDCS-1020
nRST_nSTBY nROW nFRAME_nSYNC NC NC 22 16 nIRQ NC Analog Analog Digital Digital Vdd GND GND Vdd 3, 20, 2, 19, 5, 12, 4, 11, 17 28 27 18 3.3V Regulator 3.3V Regulator
Serial Interface
Host System
Star Ground
Typical Electrical Specifications
Part Number Pixel size Maximum Clock Rate Effective Sensor Dynamic Range Effective Noise Floor Dark Signal [1,4] HDCS-2020 (VGA) 7.4 x 7.4 m 25 MHz (VGA) 65 dB (VGA) 43 e240 e-/sec (@ 22C) 1.1 V/(Lux-S) 33% 1.22 V 68,000 e17 V/e1- 40 (8 bit resolution) 42% 0.5 sec minimum, 0.5 sec increments 3.3 V, -5%/+10% 3.6 V 3.6 V 150 mW operating, 150 W standby 200 mW operating, 3.3 mW standby 1/3" -5 to +65C -40 to +125C HDCS-1020 (CIF) 7.4 x 7.4 m 32 MHz (CIF) 61 dB (CIF) 43 e240 e-/sec (@ 22C) 1.1 V/(Lux-S) 33% 1.22 V 68,000 e17 V/e1- 40 (8 bit resolution) 42% 0.5 sec minimum, 0.5 sec increments 3.3 V, -5%/+10% 3.6 V 3.6 V 150 mW operating, 150 W standby 200 mW operating, 3.3 mW standby 1/4" -5 to +65C -40 to +125C
Sensitivity [2,3] Peak Quantum Efficiency [1,2,3] Saturation Voltage Full Well Capacity Conversion Gain [2] Programmable Gain Range Fill Factor Exposure Control Supply Voltage Absolute Max. Power Supply Voltage Absolute Max. DC Input Voltage (any pin) Power Consumption (typical) Power Consumption (max) Optical Format Operating Temperature Storage Temperature Notes: 1. Specified over complete pixel area 2. Measured at unity gain 3. Measured at 555 nm 4. Excludes dark current shot noise
5
HDCS Sensor Top Level Block Diagram
Image Array VGA 640 x 480 CIF 352 x 288
Two-Wire Serial/ UART
Clock
Timing Controller
Programmable Amplifier
Programmable Amplifier
Programmable Amplifier
Analog to Digital Converter
Sync/IRQ
8/10 Digital Output
HDCS-2020 32 Pin Package Diagram
nRST_nSTBY SDATA_TxD SCLK_RxD AGND3
HDCS-1020 32 Pin Package Diagram
nRST_nSTBY
25 24 IMODE0 IMODE1 nIRQ_nCC nFRAME_nSYNC AVDD1 AGND1 GND1 VDD1 8 9 16 17
SDATA_TxD
SCLK_RxD
DATA8
DATA9
AGND3 DATA0
DATA6
DATA7
nROW
PVDD
32 1 DATA7 AGND2 AVDD2 VDD3 GND3 DRDY CLK DATA6 8 9
25 24 IMODE0 IMODE1 nIRQ_nCC nFRAME_nSYNC AVDD1 AGND1 GND1 VDD1 17 16
DATA5 AGND2 AVDD2 VDD3 GND3 DRDY CLK DATA4 1
32
DATA3
DATA2
DATA1
VDD2
nTRISTATE
GND2
nROW
PVDD
DATA5
DATA4
DATA3
DATA2
DATA1
6
DATA0
VDD2
GND2
NC
HDCS-2020 Pin Description Pkg Pins
23 24 7 25 31, 32, 1, 8, 9, 10, 13, 14, 15, 16 6 30 29 21 26 22 17, 11, 4 18, 12, 5 28 20, 3 19, 2, 27
Signal Name
IMODE1 IMODE0 CLK nRST_nSTBY Data 9, Data 8,... Data 1, Data 0 DRDY SDATA_TxD SCLK_RxD nFRAME_nSYNC nROW nIRQ_nCC VDD GND PVDD AVDD AGND
Type
Input Input Input Input Output Output Input/output open drain Input Output Output Output VDD GND PVDD AVDD AGND
Description
If = 1, Half duplex UART slave interface mode If = 0, Synchronous serial slave interface mode Always = 0 System Clock Active low system reset input and stand-by mode input Parallel digitized pixel data out Data valid for parallel digitized pixel data out Serial output data Transfer clock / serial data input Signals end of frame Signals end of row Programmable interrupt request Digital power supply Digital ground Array power supply Analog power supply Analog, array, and substrate ground
HDCS-1020 Pin Description Pkg Pins (Location)
23 24 7 25 31, 32, 1, 8, 9, 10, 13, 14 6 30 29 21 26 22 17, 11, 4 18, 12, 5 28 20, 3 19, 2, 27 15 16
Signal Name
IMODE1 IMODE0 CLK nRST_nSTBY Data 7, Data 6,... Data 1, Data 0 DRDY SDATA_TxD SCLK_RxD nFRAME_nSYNC nROW nIRQ_nCC VDD GND PVDD AVDD AGND nTRISTATE NC
Type
Input Input Input Input Output Output Input/output open drain Input Output Output Output VDD GND PVDD AVDD AGND Input NC
Description
If = 1, Half duplex UART slave interface mode If = 0, Synchronous serial slave interface mode Always = 0 System Clock Active low system reset input and stand-by mode input Parallel digitized pixel data out Data valid for parallel digitized pixel data out Serial output data Transfer clock / serial data input Signals end of frame Signals end of row Programmable interrupt request Digital power supply Digital ground Array power supply Analog power supply Analog, array, and substrate ground Disables sensor tristate mode No connect
7
Packaging General Package Specs * 32 J-leads (8 per side) * Package dimensions, optical center shown in diagram below
1.65
13.36
1.955
4.120
optical center package center
1.735
2.37
2.67 HDCS-1020 3.340 4.127 HDCS-2020 3.082
14.80
13.80
13.60
13.00
12.365
12.165 2.00 0.25 Notes: Leadframe Plating: Ni-Pd-Au Dimension Tolerances: 0.075 Leadframe Tolerances: 0.2 1.02 11.56
1.65
1.175 3.80 2.23
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. February 20, 2001 5988-2026EN

▲Up To Search▲

Price & Availability of HDCS-1020

	To Download HDCS-1020 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .